Discussion in 'BIOS Mods' started by curriegrad2004, Nov 13, 2009.
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Well, with coreboot+SeaBIOS you can add arbitrary ACPI tables easily during compilation. It's probably a 5-line patch to add this to the source code if you have a preexisting SLIC table.
Here you can try to find this patch
Is there a few words description how to add a SLIC and verify its actually there?
yes it does. but we dont advocate it. we neither promote it nor advocate it. i am using coreboot in 4 of my laptops. i got no desktop. and a happy FOSS user. moment i introduce M$ or @pple into the scene things go loose. we have more problems than solutions. you can do loads with coreboot. i am currently working on these
t60*3 (4 MiB flash), coreboot takes 64K and rest of 4 MiB is empty. planning to load kernel straight off the chipset.
x60*1 (4 MiB flash), ^^
#1. To boot of linux kernel or netbsd kernel straight of the bios chip, (NetBSD because its more desireable)
#2. Let grub2 handle the signed kernel machanism with 4096 bit key infrastructure.
#3. Let the kexec boot the rest via sd card or u-sd card.
#4. Let it be very compressed with lzma
#5. We dont wish to include vga bios, because we dont trust it. ron minnich is working on the vga replacement.
#6. we seriously dont wish to include slic x.x to facilitate inclusion of M$ and lastly if one thing goes wrong. hell breaks loose.
Catch us on #coreboot@freenode
What if someone already has a SLIC 2.1 signature in his original BIOS?
To then not include it in a Coreboot solution would mean loss of a (paid for) feature, wouldn't it?
I have thought of Coreboot myself, but I see no advantage to using it whatsoever, since I rarely use Linux. And when I do use Linux (Puppy Linux live CD or USB stick), the built in BIOS is no problem.
Also, I haven't seen any noteworthy expanded features in Coreboot, compared to BIOS or UEFI. OK, you can use your serial port (RS-232) as an output for kernel or POST messages, but that's antiquated. Most computers today lack such ports entirely.
Maybe we should ask people for a wishlist?
I would wish some kind of bolt-on expansion to the ordinary functions of the Seabios, maybe loaded from some protected part of the HDD, that would give the user something similar to UEFI. Mouse, menues, a web browser. I would love to have any ISO image stored somewhere on the Internet which I could boot with such a function.
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Interesting. I thought they had some kind of way to prevent this up-sizing of the flash chip.
Would you care to share with us, hands-on, your experiences in this field? Perhaps a tutorial?
I have found that including a SLIC 2.1 signature is supported in Coreboot, and easily at that.
It would be really interesting to get a first hand report from someone like you, who has done this, from configuration to flashing.
Maybe you could explain one thing about CorebootI simply can not understand?
The Coreboot folks say they can't support some chipset because they haven't got the data sheets for said chipset. At the same time, that same chipset works nicely in all Linux distributions? That would imply there's a driver for it and that in turn implies that the driver programmer knows something about how that particular chipset works.
What am I missing here?
What i can understand is? you guys are talking business. Now you are talking business. :-D well then fair enough. i took a little of ezh2o from this forum to get a task done since i wanted it badly then, i.e. windows server 2008. now its time to contribute back to the forum. of course open source.
well i can give a crash course. but that will take a few megabytes of internet real estate. now coming to can flash be upsized? short answer yes and no. long answer depends on the chipset. yes because if the replaceable chipset got everything of same order like there has to be bit by bit match in physical characteristics. you cannot just like that replace the flash to a higher capacity.
you need to check the physical characteristics like erase sector, block sector, page program and voltage and clock rate. if all these characteristics match with that of the old chip and the new chip (up sized) and the old chip pristine then you can go for, provided its supported by coreboot first. check with coreboot for your chipset and also flashrom. the flash updater.
you need to be skilled with soldering and you need buspirate and loads of love and patience. the tutorial is not ideal for this post reply. i need to start a new thread. yes slic is supported i never said no. i said we dont like it. we believe in freedom and we also respect a user sentiment.
there is nothing that you dont understand its that you never cared to pay proper attention. it slipped under your eyes. look carefully you need hawk eyes. every minute detail is precious.
we have a hard time with intel, bunch of mofo wont release the DRAM initialization. i can explain it. but this thread's scope is limited. i encourage you to start a new thread. and ask for inputs. if i dont know i will bug the heck out of ron minnich and will squeeze the info out. in every machine RAM init is the most crucial and thats the lissing link. and intel is such a big fsck up (where is the middle finger icon i cant see it) that they refuse to release the dram init part. if they release it then its very easy. a little ehci debug and poking the nuts here and there. and jingo baaah! this is beyond ring 0 this is ring -3, the brain the heart the soul and the mind of a pc/laptop, the cpu and its binding with the ram initialization. extremely complicated and dangerous. this is not about drivers. what you do here will govern the drivers in the future. this is the meanest part of the whole game. are you ready to play? thats the trillion US$ question. deep deep deep!
and tutorial? it will be specific to t60 and x60 and z60 only. i can white a whole tut and also i cannot supply with a ready made one, you see lenovo may be watching us:-D or may be intel, this is hard business. this is no longer tied to M$. M$ is an obsolete enemy. are you prepared to irk these giants. they are way meaner than M$. M$ is a midget. you need detailed info + mother board schematic + bus pirate (mandatory) + soic 8 clips for programming (mandatory) + understand memory mapping + upped size flash chip and their data sheets + existing flash chip data sheets + time and frustration + loads of love for the machine. else my warning it will be a charred machine. most elegant and expensive paper weight. you sure you wish to do it? or you wish to
"You take the blue pill, the story ends, you wake up in your bed and believe whatever you want to believe. You take the red pill, you stay in Wonderland, and I show you how deep the rabbit hole goes."
So if I stick to a flash rom chip from the same manufacturer and family, I should be OK?
A twice as big capacity chip will then differ by simply having one added A (address) signal. Provided that that A signal isn't tied to GND or +5V, (meaning 0 or 1) on the chip socket, and provided that the extra A signal is drawn all the way to the PLCC from its source, we have double capacity. Quadruple capacity is achieved in the same manner by adding yet another A signal. Every added A signal doubles the capacity. That's for parallell chips, serial i don't know.
The DRAM initialization isn't a field many people are very versed in, me included. But isn't that provided by the proprietary BIOS and can't that initialization be audited somehow? Yes, that would be reverse engineering, but then perhaps no data sheet would be necessery.
A tutorial on your Lenovo T60 would be nice indeed. I don't think Lenovo would object. You're using a product you own. They made it, you bought it. Like if say VW would have something to say about you modifying a Golf in some way. Why would they?
I don't see MS as an enemy.
sorry bruh, i been busy a lot and thats why this late reply.
coming to answering you, i hope this still helps you.
if you are using flashrom? then check the supported chipsets. you can then solder it onto the board. and then use the programmer like buspirate to program it.
doubling is easy, but there is a limit 16 MB max. so if i were you i would choose my chips carefully. and second in thinkpad t60 and x60 i have seen only spi bios chips only.
"The DRAM initialization isn't a field many people are very versed in, me included. But isn't that provided by the proprietary BIOS and can't that initialization be audited somehow? Yes, that would be reverse engineering, but then perhaps no data sheet would be necessery."
more than that, you need to know someone from intel, ready to co-operate, which i doubt, and secondly, you need a intel cpu jtag, wich is pricey, nearly 5000 US$. and worst is each jtag is designed specifically for a set of pins, line pbga, ppga etc etc. i hope you get the idea. if the pin is for pbga then you cant use it for ppga. sucks! screw intel.
"A tutorial on your Lenovo T60 would be nice indeed. I don't think Lenovo would object. You're using a product you own. They made it, you bought it. Like if say VW would have something to say about you modifying a Golf in some way. Why would they?" difficult online in a forum like this. from may 1 st i will be in freenode. nick : dumbo101, catch me in freenode..... catch me in irc. and also if you need some specific help related to compiling and et al let me know.
M$ doesnt like coreboot. they are headbent on pushing us away. which is why M$ and we dont mix well.
and figaro once again i am sorry for posting this late, i been s**t ass busy with porting coreboot to n900, t410, t420 and t430. i hope you will excuse me.